online read us now
Paper details
Number 2 - June 2023
Volume 33 - 2023
Technology mapping of multi-output functions leading to the reduction of dynamic power consumption in FPGAs
Adam Opara, Marcin Kubica
Abstract
This article presents a synthesis strategy aimed at minimizing the dynamic power consumption of combinational circuits
mapped in LUT blocks of FPGAs. The implemented circuits represent the mapping of multi-output functions. Properly
selected multi-output functions are described using a new form of the binary decision diagram (BDD), which is an extension
of pseudomulti-terminal BDDs (PMTBDDs) in the literature. The essence of limiting power consumption is to include
additional parameters during decomposition, such as the switching activity associated with the switching PMTBDD (SWPMTBDD). In addition, we highlight the key importance of circuit optimization methods via non-disjoint decomposition
when minimizing power consumption. An algorithm is proposed to assess the effectiveness of decomposition, considering
several parameters, such as the number of non-disjoint decompositions as well as that of shared and non-shared bound
functions or the switching activity. The results of experiments that demonstrate the effectiveness of the proposed methods
are also included.
Keywords
low power synthesis, FPGA, switching activity, decomposition, technology mapping